Fabrication of integrated circuitry typically involves forming contact openings through an insulative layer to an elevationally lower substrate node location, such as a diffusion region which constitutes part of a field effect transistor. Typically, field effect transistors are fabricated on a semiconductor wafer, with selected individual transistors being separated by isolation oxide or field oxide regions. As integrated circuitry dimensions grow smaller and smaller, challenges are presented with respect to the formation of contact openings to substrate node locations.
For example, one type of integrated circuitry is a dynamic random access memory device which includes a plurality of isolation oxide regions over which conductive word lines extend. Conductive word lines are usually covered or insulated with protective nitride caps and sidewalls. A thick layer of oxide typically overlies the word lines. A contact opening etch can be conducted selective relative to the protective caps and sidewalls to achieve self-alignment of the contact opening in a direction perpendicular to the line. However, because such word lines typically overlie isolation oxide regions, and because the insulative layer through which the contact opening is etched usually etches in the same manner as the material from which the isolation oxide regions are formed, e.g. when both are oxides, a problem arises insofar as undesirably etching into the isolation oxide region when the contact openings are formed.
This invention arose out of concerns associated with improving the manner in which contact openings are formed in integrated device fabrication.